In some applications it is necessary to switch between two clock signals where one clock signal is provided by a first source and is used for one purpose, and the other clock signal is provided by a second source and is used for another purpose. Most specifications for providing a clock signal to integrated circuits specify a clock signal must be high for a minimum period of time and low for a minimum period of time to assure that operations initiated by each cycle of a clock signal are completed before the occurrence of a subsequent clock cycle. In switching from a first clock source to a second clock source, it is imperative that the clock signal not violate the specifications. For a clock signal to be maintained in either state, high or low, for an extended period of time, does not violate the specifications. To have a high or low portion of any clock signal cycle that is less than the specified minimum, called a glitch, is undesirable.
One such application is a disk drive read channel where it is desired to switch between two clock signals that have arbitrary frequency and phase relationships. When data is being written onto a disk, a clock signal generated by a local crystal oscillator is utilized. The disk is a spinning magnetic medium with the potential of having slight variations in the speed of rotation. When data is being read from the disk, a phase-locked loop circuit is utilized to recover a clock signal from the read data as it is being read from the disk because of the potential variations in disk speed both during the read and write operations. The read and write data is transferred to and from a controller that communicates with a computer to further process the data. This data transfer must be accomplished using a clock with the correct phase and frequency relationship to the data being transferred. In switching from reading to writing operations or from writing to reading operations, the clock switching must be glitch free or the disk drive controller might be switched to an unpredictable state.
It would be desirable to have a multiplexer that would switch from a first clock signal to a second clock signal in a manner that assures that neither the high portion nor the low portion of any clock cycle is shortened.